1. Field of the Invention
The present invention is concerned with an arrangement for detecting defects in static random access memories, and in particular although not exclusively with an arrangement for detecting open circuit or "soft" defects in six-transistor memory cells.
2. Description of the Related Art
In large memories over half the area of a chip may be taken up by the array of memory cells, and in order to allow for the occurrence of defects a number of spare circuits or memory cells may be provided on the chip so that during testing any failed circuit or block of memory cells may be replaced by a spare, for example by blowing fuse links, in order to minimize the number of chips rejected.
With advances in technology it is now possible to integrate large amounts of memory into complex systems on single chips, and the costs involved in producing such a system depend increasingly on the defect levels in the embedded memory, and its area and test requirements can be the dominant factors. The use of the comprehensive test and redundancy techniques employed for standard memory chips makes little sense in embedded applications, since the cost of these techniques is justified only by high volume production and little variation in product. The wider the range of designs using external testing and fuse techniques, to more time and effort is required to characterize and implement specific schemes for each variant.
Self testing of memories is now employed in embedded systems to reduce test cost. However, one of the major problems is testing for retention failure and open circuits, which still require tests to be done externally.